NXP Semiconductors /LPC43xx /UART1 /FDR

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Interpret as FDR

31282724232019161512118743000000000000000000000000000000000000000000DIVADDVAL0MULVAL0RESERVED

Description

Fractional Divider Register. Generates a clock input for the baud rate divider.

Fields

DIVADDVAL

Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate.

MULVAL

Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not.

RESERVED

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

Links

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